1. Field of the Invention
The present invention generally relates to phase change memory devices, and more particularly, the present invention relates to phase change memory devices and methods of driving word lines of phase change memory devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0039721, filed May 12, 2005, in the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.
2. Description of the Related Art
Phase change random access memories (PRAMs) are non-volatile memory devices that store data using a phase change material, e.g., Ge—Sb—Te (GST). The phase change material, which exhibits different resistive values depending on the crystalline or amorphous phase thereof, is programmed by thermal treatment to set the phase of the material.
FIG. 1 illustrates an example of an equivalent circuit diagram of a unit memory cell C of a conventional phase change memory device. As shown, the unit memory cell C includes a P-N diode D and a phase change element GST connected in series between a bit line BL and a word line WL. In this example, the phase change element GST is connected between the bit line BL and a p-junction of the diode D.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
In a read operation, a given read current is provided to a selected memory cell, and the “1” or “0” resistive state of the memory cell is discriminated based on a voltage of the cell.
FIG. 2 is a simplified circuit diagram of a phase change memory device. As shown, the phase change memory device 100 includes a memory cell array CBLK, word line drive (WD) circuits 10-0˜10-n−1, a bit line selection circuit 15, and peripheral circuits 17. Although not shown, the peripheral circuits 17 generally include a write driver circuit, a sense amplifier, and a data I/O buffer. The memory cell array CBLK includes an array of unit memory cells connected between corresponding bit lines BL0˜BLm−1 and word lines WL0˜WLn−1.
The bit line selection circuit 15 includes transistors for respectively selecting the bit lines BL0˜BLm−1 in response to selection signals YL0˜YLm−1.
In the examples given herein, a bit line is “selected” by changing its voltage to a high level, whereas a word line is “selected” by changing its voltage to a low level. In contrast, “non-selected” bit lines have a low level voltage, and “non-selected” word lines have a high level voltage.
FIG. 3 is a circuit diagram of the word line drive circuit 10-0 shown in FIG. 2. The remaining word line drive circuits 10-1˜10-n−1 are similarly configured.
The word line drive circuit 10-0 includes a first NMOS transistor N1 connected between a ground voltage VSS and the word line WL0, and a first PMOS transistor P1 connected between the word line WL0 and a power voltage VCC. The gates of the transistors N1 and P1 are connected to receive a decoded signal DS from a row decoder (not shown).
Referring back to FIG. 2, assume that the unit memory cell at the intersection of word line WL0 and bit line BL1 is to be selected for writing or reading. In this case, the selected bit line BL1 is driven to a high level voltage and the remaining non-selected bit lines BL0, BL2˜BLm−1 are driven to a low level voltage. On the other hand, the selected word line WL0 is driven to a low level voltage and the remaining non-selected word lines WL1˜WLn−1 are driven to a high level voltage.
Referring additionally to FIG. 3, in order to select the word line, a high level decoded signal DS is applied to the word line driving circuit 10-0 so as to turn on the first NMOS transistor N1 and turn off the first PMOS transistor P1. As such, the selected word line WL0 goes to a low level. The decoding signal DS is a low level signal with respect to the remaining word lines WL1˜WLn−1, and accordingly, the first PMOS transistor P1 is on and the first NMOS transistor N1 is off in each of the remaining word line drive circuits 10-1˜10-n−1. As such, the remaining word lines WL1˜WLn−1 are driven to a high level.
The phase change memory device described above suffers a drawback in that leakage current can result from maintaining each of the non-selected word lines WL1˜WLn−1 at a high level. In particular, excessive power is consumed as a result of the leakage current that occurs during a standby mode of the phase change memory device.